1. Field of the Invention
The present invention relates to a semiconductor device including a vertical MOSFET having a trench gate structure.
2. Description of Related Art
For example, a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field Effect Transistor) with a trench gate structure is known as a power MOSFET having low ON resistance characteristics.
For example with a semiconductor device including an N-channel VDMOSFET having a trench gate structure, an N-type epitaxial layer is laminated on an N+ (high concentration N)-type substrate. A P-type body region is formed in a top layer portion of the epitaxial layer. A trench is formed by digging in from a top surface of the body region. In the trench, a gate electrode is embedded via a gate insulating film. Further, an N+-type source region and a P+ (high concentration P)-type body contact region, penetrating through the source region in a thickness direction, are formed in a top layer portion of the body region. By grounding the source region and the body contact region and controlling a potential of the gate electrode while applying a positive voltage of a suitable magnitude to a drain electrode formed on a rear surface of the N+-type substrate, a channel is formed near an interface of the gate insulating film (trench) in the body region and a current flows between the source region and the drain electrode.
With this type of VDMOSFET, a layout design of the trenches (gate electrodes) is being examined to enlarge a channel area per unit cell area and thereby reduce an ON resistance.
FIG. 4 is a schematic plan view of a layout of gate electrodes and body contact regions in a conventional semiconductor device.
With the conventional semiconductor device, a plurality of body contact regions 41 are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions 41 aligned in a predetermined direction Y (referred to as the “column direction Y” hereinafter in this section), gate electrodes 42 are disposed at both sides in a row direction X orthogonal to the column direction Y. Each gate electrode 42 extends in the column direction Y and is bent at right angles repeatedly and alternately to respective sides in the row direction X so that gaps D, equivalent to a width in the row direction X of the body contract region 41, are formed in the row direction X between the gate electrodes 42 and the gate electrodes 42 that are adjacent in the row direction X and between the gate electrodes 42 and the body contact regions 41.
With this configuration, in comparison to a configuration where body contact regions are formed in an array in a plan view and rectilinearly extending gate electrodes are formed between respective columns formed by the body contact regions that are aligned in the column direction, a gate width (total length of a gate in a plan view) in a single unit cell is increased in correspondence to the bending of the gate electrodes and the channel area per unit cell area is thus increased. The ON resistance can thus be reduced.
However, because the structure shown in FIG. 4 has corner portions due to the bending of the gate electrodes 42 at right angles, when a stress is applied to the semiconductor device, the stress may concentrate at the corner portions and cause disconnection of the gate electrodes 42.